This invention relates to digital-to-pulse width converters, and more particularly to a digital-to-pulse width converter that provides a pulse width output that is divided up into a series of pulses that are distributed across the entire time period of the pulse width output.
Digital-to-pulse width converter circuits are commonly used as part of a circuit that, inexpensively converts a digital number to an analog value. The digital-to-pulse width converter circuit uses a single digital output pin to provide a binary logic level, pulse width signal that is proportional to a digital value (i.e., a desired set-point), the set-point being comprised of a plurality of binary digits ("bits"). An analog circuit, such as an integrator, then converts this pulse width binary signal to an analog voltage or current.
The resolution of the digital-to-pulse width converter is the number of different pulse width values that can be commanded by all possible set-points. A four bit digital set-point value allows sixteen different pulse width outputs; a sixteen state resolution. A five bit digital value allows for 32 different pulse width outputs; a 32 state resolution. For a fixed clock frequency input to the counter, the cycle time increases as the number of bits in the digital value increases. Adding one bit to the digital set-point value doubles not the resolution, but also the cycle time of the converter. This longer cycle time increases the response time of the counter, which is the time measured from the changing of the set-point to the pulse width output achieving the value commanded by the set-point. This longer cycle time may also increase the amount of ripple in the corresponding analog voltage or current output of the integrator.
Ripple is the amount of undesirable fluctuations in the amplitude of the integrator analog output signal. A smooth transition, relatively free of fluctuations, is desired as the analog output signal transitions between the previous set-point value to the new commanded set-point value. Also, it is desired that the integrator output signal have as little ripple as possible as the integrator integrates the current set-point value. Ripple can be eliminated during analog output signal transitions between old and new set-point values by selection of an appropriate time constant. However, there usually is some small amount of ripple in the integrator output signal as it integrates the constantly changing binary logic levels of the pulse width output signal for any current set-point value. That is, there are small fluctuations of the integrator analog output signal around the "steady-state" value that corresponds to the current set-point value.
A problem with prior art digital-to-analog converters that use a digital-to-pulse width conversion scheme is that when the digital set-point changes, the integrator takes a finite amount of time to integrate the pulse width output. That is, the integrator output does not change in a step-like, instantaneous manner. This is because the time constant of the integrator cannot be made arbitrarily small because the integrator must integrate the pulse width output adequately to achieve a relatively ripple-free integrator output signal. If the pulse width output signal was at a higher frequency, the integrator time constant could be made smaller, speeding up the response time of the integrator.
It is known in the prior art to divide up the pulse width output of a digital-to-pulse width converter into a series of pulses. This pulse width "distribution" method effectively increases the frequency of the pulse width output, which allows for use of an integrator with a lower time constant. This has the desirable result of reducing the response time of the analog output to the digital input. However, the time constant of the integrator is still set to a sufficiently long value such that a small amount of ripple is introduced into the integrator output during integration of the current set-point value.
Examples of prior art pulse width "distribution" methods are described in U.S. Pat. Nos. 4,233,591 and 4,590,457. However, both of these patents describe distribution methods that involve the addition of complex digital pulse distribution circuitry to the existing, relatively simplistic circuitry of a digital-to-pulse width converter. Also, both patents do not provide for an "optimum" distribution or dividing up of the pulse width output. An optimum distribution is one in which the pulse width output has been divided into a plurality of pulses that are distributed as evenly and equally as possible over the entire pulse width time period, taking into account all of the possible combinations of the distributed pulse width output signal.
Accordingly, it is a primary object of the present invention to provide a digital-to-pulse width converter having a pulse width output that is divided into a plurality of pulses that are distributed in an optimum configuration across the entire time period of the pulse width output.
It is general object of the present invention to provide a digital-to-pulse width converter, with a distributed binary pulse width output, which significantly reduces the complex additional circuitry required by prior art pulse width distribution schemes.
It is a further object of the present invention to provide a digital-to-pulse width converter, with a distributed binary pulse width output, which responds faster to selected digital set-point values because of the optimum distribution of the pulse width output.
It is still another object of the present invention to provide a digital-to-pulse width converter, with a distributed binary pulse width output, having an integrator for converting the pulse width output into an analog signal, the optimum distribution of the pulse width output allowing for a smaller time constant for the integrator, thereby decreasing the response time of the integrator.
It is yet another object of the present invention to reduce the amplitude of the ripple voltage in the integrator output signal as the integrator is integrating the currently-selected set-point value as indicated by a series of binary logic level pulses at the pulse width output.
The above and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.